CMOS (Complementary Metal-Oxide Semiconductor) imagers are increasingly being used as low cost imaging devices. A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least pixel selecting field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of a transistor coupled to the pixel selecting transistor. The charge storage region may be constructed as a floating diffusion region. The imager may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a so-called four-transistor (4T) CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing a reset voltage and a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, all assigned to Micron Technology, Inc. The disclosures of each of the foregoing are hereby incorporated by reference herein in their entirety.
Trench isolation regions are an essential part of current fabrication methods for CMOS and other microelectronic circuits. The decreasing dimensions of devices and the increasing density of integration in microelectronic circuits have required a corresponding reduction in the size of isolation structures. This reduction places a premium on reproducible formation of structures that provide effective isolation, while also occupying a minimum amount of the substrate surface.
One isolation technique widely employed in semiconductor fabrication is the shallow trench isolation (STI) region. The STI technique forms trench isolation regions that electrically isolate the various active components formed in integrated circuits. In the STI technique, the first step is the formation of a plurality of trenches at predefined locations in the substrate. This occurs usually through anisotropic etching. After the etching is complete, the trenches are filled with an oxide to complete the STI structure. One major advantage of using the STI technique over the conventional LOCOS (Local Oxidation of Silicon) insulation technique is the high scalability to CMOS IC devices for fabrication at the sub-micron level of integration. Another advantage is that the STI technique helps prevent the occurrence of the so-called “bird's beak” encroachment, which is characteristic to the LOCOS technique.
In order to provide context for the present invention, a portion of a conventional CMOS image sensor cell 10 is illustrated in FIG. 1. As described in general terms above, incident light causes electrons to accumulate in an n-type region 26 of a photodiode 21. An output signal, which is produced by the source follower transistor having gate 50, is proportional to the number of electrons extracted from the n-type region 26.
Trench isolation regions 15 having sidewalls 16 and a bottom 17 are formed in a p-well active layer 94 and adjacent to the charge photodiode 21, to isolate the cell 10 from adjacent pixel cells. Trench isolation regions 15 are formed using known STI techniques. Specifically, the trenches 15 are etched by employing a dry anisotropic or other suitable etching process, and are filled with a dielectric such as a chemical vapor deposited (CVD) silicon dioxide (SiO2) or other known oxide. The filled trenches 15 are then planarized so that the dielectric remains only in the trenches and their top surface remains level with that of the silicon substrate 20.
As scaling continues to decrease the size of each device, such as pixel cell 10, isolation techniques become increasingly important. Traditional STI fabrication methods have several drawbacks that are intensified by desired scaling. STI regions, such as trench 15, have encountered processing problems such as void prevention, corner rounding, and gap fill. Several techniques have been devised in order to mitigate these negative effects which tend to reduce the isolation capabilities of the STI regions.
Another problem that pixel cells encounter due to scaling occurs when the spacing between the active areas of the pixels is decreased. The effect of the decrease in area is illustrated in FIGS. 2A, 2B, and 2C. When adjacent active areas of a pixel cell, which can be multiple areas within a cell or of adjacent cells, are supplied with different voltages, an electric field is created between the two areas. These electric fields are generally shown in the accompanying drawings, which illustrates that the field may take on many forms depending on the voltage levels applied (see, e.g., Fields F1, F2, and F3). This field, in turn, may provide transportation of electrons between the two active areas. Electrons may even be carried through an isolation region, as typical isolation regions do not block this flow. This undesirably reduces the quantum efficiency of the pixel cell.
There is needed, therefore, an isolation region for use in imager pixels that prevents an electric field penetration between active areas of adjacent pixels without reducing the quantum efficiency of the pixels. There is also a need for a simple method of fabricating the desired isolation regions in pixels.